Deep trench capacitors are used in a variety of semiconductor chips for high areal capacitance and low device leakage. Typically, a deep trench capacitor provides a capacitance in the range from about 4 fF (femto-Farad) to about 120 fF. A deep trench capacitor may be employed as a charge storage unit in a dynamic random access memory (DRAM), which may be provided as a stand-alone semiconductor chip, or may be embedded in a system-on-chip (SoC) semiconductor chip. A deep trench capacitor may also be employed in a variety of circuit applications such as a charge pump or a capacitive analog component in a radio-frequency (RF) circuit.
Semiconductor-on-insulator (SOI) devices formed on an SOI substrate or on a hybrid substrate provide high performance in advanced semiconductor chips. In SOI devices, the capacitive coupling between a substrate and semiconductor devices is reduced by the presence of a buried insulator layer. By forming a deep trench capacitor in the SOI substrate, SOI logic devices such as SOI transistors and deep trench capacitors may be formed on the same SOI substrates thereby enabling embedding of deep trench capacitors into the SOI substrate that also contain high performance SOI logic devices. Such embedded deep trench capacitors enable various functionality including embedded dynamic access memory (eDRAM) and other embedded electronic components requiring a capacitor.
High performance SOI devices employ an SOI substrate having a thin top semiconductor layer having a thickness from about 3 nm to about 100 nm. Such an SOI substrate is referred to as an ultrathin SOI (UTSOI) substrate. Despite such enhanced performance, however, such UTSOI substrates presents a difficulty in the formation of a buried strap employed to electrically connect the deep trench capacitor to an access transistor, which is required in an embedded DRAM cell or other devices in which electrical connection to the deep trench capacitor is controlled by an access transistor.
Specifically, difficulty in recess control of a conductive fill material arises as the thickness of a top semiconductor layer is reduced below the 100 nm range. On one hand, if the recess depth of the conductive fill material falls below the bottom surface of the top semiconductor layer, or an “UTSOI layer,” the conductive fill material does not make contact with the top semiconductor layer, and as a consequence, the inner electrode of the deep trench is electrically disconnected from the access transistor in the top semiconductor layer. On the other hand, if the recess depth is less than a minimum distance below the top surface of the top semiconductor layer, the thickness of the portion of a shallow trench isolation structure above the buried strap comprising the conductive fill material decreases below a minimum value. In this case, the leakage current between a passing word line over the shallow trench isolation structure and the buried strap increases to degrade the performance of the device incorporating the deep trench capacitor or even render the device non-functional.
In view of the above, there exists a need for a semiconductor structure incorporating a deep trench capacitor having a reliable and stable contact between the inner electrode of the deep trench capacitor and an access transistor in a semiconductor-on-insulator (SOI) substrate and methods of manufacturing the same.
Further, there exists a need for a semiconductor structure incorporating a deep trench capacitor having a buried strap structure providing stable and process-variation-independent electrical contact between the inner electrode and the access transistor in a semiconductor-on-insulator (SOI) substrate having an UTSOI layer and methods of manufacturing the same.